Chip Design & Verification Engineer (Part-Time W-2)

Engineering • W-2 Part-Time • Remote (US) • 20–40 hrs/week

JobHub by NeonLabs is partnering with Mercor and Cincinnatus LLC to help a leading AI lab's cutting-edge GenAI team grow a group of chip design and verification engineers who shape how its models understand real hardware engineering work.

If you've spent your career chasing down a bug across multiple blocks, architected a piece of RTL from scratch, or fought a design through timing and coverage closure, this team wants your judgment. We're building this out across experience levels, from PhD students and new grads just starting out to senior engineers who've taken silicon all the way to tapeout — what matters is that you've actually done the work, not just studied it.

⚙️ What You'll Do

• Design and write up realistic chip engineering problems drawn from your own experience — the kind of design, debugging, or verification work you've actually done, not textbook exercises.
• Build out full solutions to go with them: reference RTL, testbenches, and supporting materials, using SystemVerilog/Verilog and the tools you already know.
• Run your problems against an AI model, see where it holds up and where it doesn't, and help explain why.
• Work alongside other engineers on the team to keep everyone's work at a consistent bar of rigor and difficulty.

🧠 Ideal Qualifications

• Hands-on ASIC/SoC design and/or functional verification experience, ideally with exposure to production silicon that's been taped out.
• Strong fluency in SystemVerilog/Verilog.
• Comfortable working in industry toolchains (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi) and/or their open-source counterparts (Icarus Verilog, Verilator, CocoTB, Yosys, OpenROAD).
• Solid grasp of subsystem/SoC-level concerns: interface protocols, handshaking and backpressure, multiple clock domains, and multi-module dataflow.
• Real depth in at least one of: RTL design & microarchitecture; IP integration, bring-up & system configuration (NoC, PCIe, DDR, ARM/AXI); functional verification (UVM, SVA, CocoTB; testbench architecture); formal verification & coverage closure; PPA, timing, and synthesis optimization; analog/mixed-signal design verification; or specification authoring, comprehension & Q&A.
• Able to commit 20–40 hours per week, with confirmed availability and no scheduling conflicts.
• Nice to have: past experience in AI training, model evaluation, or data annotation.
• Strong written communication and comfortable working independently.

💡 What Makes This Role Unique

• Bring real-world chip engineering judgment directly into how a leading AI lab trains and tests its frontier models.
• No single "right" background — PhD students, new grads, and tapeout-tested senior engineers are all being considered.
• Flexible part-time engagement that fits around your existing schedule.
• Work alongside a team of engineers holding each other to a consistent bar of rigor and difficulty.

💰 Engagement Details

• Pay: Competitive hourly rate (USD, based on experience)
• Employment Type: W-2 Part-Time Role via Cincinnatus LLC (Employer of Record), with placement at a leading AI lab as part of its extended workforce
• Schedule: Roughly 20–40 hours per week, depending on your availability
• Location: Fully Remote — United States only 🇺🇸
• Residency Requirement: United States
• Opportunity: New opportunity with ongoing potential for continued engagement

📋 Application Process

• Submit your resume and relevant background in chip design, verification, or related silicon work.
• Applications reviewed on a rolling basis.
• Shortlisted engineers will complete a structured technical review.
• Typical response time: within one week of submission.